Titlebook: Dry Etching Technology for Semiconductors; Kazuo Nojiri Book 2015 Springer International Publishing Switzerland 2015 3D Integrated Circuit

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Dry Etching of Various Materials,/poly–Si gate. Once the reader understands these completely, then a similar approach may be followed for designing an etching process for shallow trench isolation (STI) and W metal lines. Also, with gate etching, there is a strong need not only to control the etch profile, but also to minimize the p

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Future Challenges and Outlook for Dry Etching Technology,ume production. This means that minimum feature sizes were scaled to 1/200 in 36 years. At the same time, the number of transistors on each microprocessor chip grew by approximately 100,000-fold. Furthermore, the Si wafer diameter, which used to be 75 mm in 1975, had grown to 300 mm. It is a differe

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Giuseppe Rossi,Bartolomeo Rejtanoin this technology. However, because the process uses plasma, the devices are susceptible to various types of damages caused by high-energy and charged particles. A large amount of damage sometimes lowers the LSI yields and reliability.

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Anna Budzanowska,Tomasz Pietrzykowskiis underpinned by various large-scale integration (LSI) devices such as microprocessors and memory. The LSI technology is advancing very rapidly, as shown in Fig. 1.1, with the device density doubling approximately every 2 years [1]. The transistor count in Fig. 1.1 refers to the number of transisto

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Islam, Europe, and the Problem of Peacebe categorized into (1) etching of Si, (2) etching of insulators, and (3) etching of metal line materials. In this chapter, the key technologies in each category—which are gate etching, SiO. etching for holes, spacer etching, and etching of Al alloy stacked metal layer structures—are described in de