Titlebook: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation; 20th International W René Leuken,Gilles Sica

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EXPEL

A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversionts for 1pf integrating capacitor and bias current of 20nA, cutoff frequency is 113.4 KHz and power consumption is 45.44nW. Integrator’s Cutoff frequency is tuned from 1.083 KHz to 1.023MHz using variable integrator capacitor value in the range of 10pf-0.1pf.

用手捏

Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuitsnovel strategy. The obtained results show that the energy efficiency and the performance of FFs is mainly determined by the regularity of their topology and layout. Finally, the area-delay tradeoff is also analyzed for the first time.

呼吸

inferno

On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFSts throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.

Motilin

L1 Data Cache Power Reduction Using a Forwarding Predictorthe data cache access– or it should catch it from the data cache. Our simulation results show that 36% data cache power savings can be achieved on average, with a negligible performance penalty of 0.1%.

CANON

Defiance

An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedon strategy is chosen and automatically applied to the source code. In comparison to the manual optimization of power peaks, the automatic approach decreases the execution time overhead while only slightly increasing the required code size.

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