Titlebook: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits; Sung Kyu Lim Book 2013 Springer Science+Business Media New Yo

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TSV-to-TSV Coupling Analysis and Optimizationg model. Analysis results show that TSVs cause significant coupling noise and timing problems despite the fact that TSV count is much smaller compared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show t

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TSV Current Crowding and Power Integrityior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This chapter studies DC current crowding and its impact on 3D power integrity. First, we explore the current density d

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Thermal-Aware Gate-Level Placement for 3D ICpread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high

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3D IC Cooling with Micro-Fluidic Channelsave been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic channel (MFC) based cooling. In case of power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level.

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