Titlebook: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits; Sung Kyu Lim Book 2013 Springer Science+Business Media New Yo

小巷

書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits影響因子(影響力)




書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits影響因子(影響力)學(xué)科排名




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書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits網(wǎng)絡(luò)公開(kāi)度學(xué)科排名




書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits被引頻次




書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits被引頻次學(xué)科排名




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書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits年度引用學(xué)科排名




書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits讀者反饋




書目名稱Design for High Performance, Low Power, and Reliable 3D Integrated Circuits讀者反饋學(xué)科排名

老人病學(xué)

Regular Versus Irregular TSV Placement for 3D IC. To solve this problem effectively, we study two TSV assignment algorithms, compare them with other TSV assignment algorithms, and analyze the impact of the quality of TSV assignment algorithms on 3D ICs. Experimental results show that the wirelength of 3D ICs is shorter than that of 2D ICs by up t

Transfusion

Steiner Routing for 3D IC. In addition, our TSV relocation results in 9% maximum temperature reduction at no additional area cost. We also provide extensive experimental results including (i) the wirelength and delay distribution of various types of 3D interconnects, (ii) the impact of TSV RC parasitics on routing and TSV r

Irrepressible

Low Power Clock Routing for 3D IChat the overall power consumption is minimized. Related SPICE simulation indicates that: (1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case; (2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network dec

coagulate

挫敗

3D Clock Routing for Pre-bond Testabilityinimum skew and constrained slew. Compared with the single-TSV solution, SPICE simulation results show that our multi-TSV approach significantly reduces the clock power by up to 15.9 % for two-die and 29.7 % for four-die stacks. In addition, the wirelength is reduced by up to 24.4 and 42.0 %..The ma

挫敗

3D IC Cooling with Micro-Fluidic Channelse goal of our holistic approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space exploration for early design stage. We also provide an in-depth comparison between T-TSV vs. MFC based cooling method and discuss how to employ DOE and RSM techniques

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WITH

General Principles of Preoperative Planning. To solve this problem effectively, we study two TSV assignment algorithms, compare them with other TSV assignment algorithms, and analyze the impact of the quality of TSV assignment algorithms on 3D ICs. Experimental results show that the wirelength of 3D ICs is shorter than that of 2D ICs by up t

CAMEO

Subcapital Fracture of Fifth Metacarpal. In addition, our TSV relocation results in 9% maximum temperature reduction at no additional area cost. We also provide extensive experimental results including (i) the wirelength and delay distribution of various types of 3D interconnects, (ii) the impact of TSV RC parasitics on routing and TSV r