Titlebook: VLSI Synthesis of DSP Kernels; Algorithmic and Arch Manesh Mehendale,Sunil D. Sherlekar Book 2001 Springer Science+Business Media New York

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Implementation of Multiplication-Free Linear Transforms on a Programmable Processor, Y are the input and the output vectors and A is the transformation matrix whose elements are 1,-1 and 0. This chapter presents optimized code generation of these transforms targeted to both register rich RISC architectures such as ARM7TDMI [6] and single register, accumulator based DSP architectures such as TMS320C2x [95] and TMS320C5x [96].

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Summary,ation opportunities were identified in the area-delay-power space targeted to technologies ranging from programmable processors to hardwired implementations with or without a hardware multiplier. The algorithmic and architectural transformations presented in this book cover this entire solution space.

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Programmable DSP Based Implementation,A programmable DSP is a processor customized to implement digital signal processing algorithms efficiently. The customization is based on the following characteristics of DSP algorithms:

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