Titlebook: VLSI Synthesis of DSP Kernels; Algorithmic and Arch Manesh Mehendale,Sunil D. Sherlekar Book 2001 Springer Science+Business Media New York

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Multiplier-Less Implementation,pace conversion kernels such RGB-to-YUV. Since the coefficients are fixed, the flexibility of a multiplier is not necessary and an efficient implementation of such transforms can be obtained using adders and shifters. This chapter presents techniques for area efficient implementation of fixed coeffi

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A Framework for Algorithmic and Architectural Transformations, different implementation styles. This chapter proposes a framework that encapsulates these transformations and enables a systematic exploration of the area-delay-power solution space. The framework is based on a classification of the transformations into seven categories which exploit unique proper

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