| 書(shū)目名稱 | VLSI Synthesis of DSP Kernels |
| 副標(biāo)題 | Algorithmic and Arch |
| 編輯 | Manesh Mehendale,Sunil D. Sherlekar |
| 視頻video | http://file.papertrans.cn/981/980103/980103.mp4 |
| 圖書(shū)封面 |  |
| 描述 | A critical step in the design of a DSP system is to identifyfor each of its components (DSP kernels) an implementationarchitecture that provides the desired degree offlexibility/programmability and optimises thearea-delay-power parameters. The book covers the entiresolution space comprising both hardware multiplier-based andmultiplex-less architectures that offer varying degrees ofprogrammability. For each of the implementation styles, severalalgorithmic and architectural transformations are proposed so as tooptimally implement weighted-sum based DSP kernels over thearea-display-power space. ..VLSI Synthesis of DSP Kernels. presents the following:. Six different target implementation styles -. . Programmable DSP-based implementation; ..Programmable processors with no dedicated hardware multiplier; ..Implementation using hardware multiplier(s) and adder(s); ..Distributed Arithmetic (DA)-based implementation; .. ResidueNumber System (RNS)-based implementation; and .. Multiplier-lessimplementation (using adders and shifters) for fixed coefficient DSPkernels. .. .. For each of the implementation styles,description and analysis of several algorithmic and architecturaltransformations aim |
| 出版日期 | Book 2001 |
| 關(guān)鍵詞 | Hardware; Signal; VLSI; algorithms; architecture; digital signal processor; software; tables |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4757-3355-6 |
| isbn_softcover | 978-1-4419-4904-2 |
| isbn_ebook | 978-1-4757-3355-6 |
| copyright | Springer Science+Business Media New York 2001 |
|Archiver|手機(jī)版|小黑屋|
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