找回密碼
 To register

QQ登錄

只需一步,快速開(kāi)始

掃一掃,訪問(wèn)微社區(qū)

打印 上一主題 下一主題

Titlebook: Sequential Logic Testing and Verification; Abhijit Ghosh,Srinivas Devadas,A. Richard Newton Book 1992 Springer Science+Business Media New

[復(fù)制鏈接]
查看: 39576|回復(fù): 40
樓主
發(fā)表于 2025-3-21 16:42:36 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書(shū)目名稱Sequential Logic Testing and Verification
編輯Abhijit Ghosh,Srinivas Devadas,A. Richard Newton
視頻videohttp://file.papertrans.cn/866/865400/865400.mp4
叢書(shū)名稱The Springer International Series in Engineering and Computer Science
圖書(shū)封面Titlebook: Sequential Logic Testing and Verification;  Abhijit Ghosh,Srinivas Devadas,A. Richard Newton Book 1992 Springer Science+Business Media New
描述In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care- fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte- gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that ther
出版日期Book 1992
關(guān)鍵詞Counter; RTL; VLSI; algorithms; computer; computer-aided design (CAD); integrated circuit; logic; manufactur
版次1
doihttps://doi.org/10.1007/978-1-4615-3646-8
isbn_softcover978-1-4613-6622-5
isbn_ebook978-1-4615-3646-8Series ISSN 0893-3405
issn_series 0893-3405
copyrightSpringer Science+Business Media New York 1992
The information of publication is updating

書(shū)目名稱Sequential Logic Testing and Verification影響因子(影響力)




書(shū)目名稱Sequential Logic Testing and Verification影響因子(影響力)學(xué)科排名




書(shū)目名稱Sequential Logic Testing and Verification網(wǎng)絡(luò)公開(kāi)度




書(shū)目名稱Sequential Logic Testing and Verification網(wǎng)絡(luò)公開(kāi)度學(xué)科排名




書(shū)目名稱Sequential Logic Testing and Verification被引頻次




書(shū)目名稱Sequential Logic Testing and Verification被引頻次學(xué)科排名




書(shū)目名稱Sequential Logic Testing and Verification年度引用




書(shū)目名稱Sequential Logic Testing and Verification年度引用學(xué)科排名




書(shū)目名稱Sequential Logic Testing and Verification讀者反饋




書(shū)目名稱Sequential Logic Testing and Verification讀者反饋學(xué)科排名




單選投票, 共有 0 人參與投票
 

0票 0%

Perfect with Aesthetics

 

0票 0%

Better Implies Difficulty

 

0票 0%

Good and Satisfactory

 

0票 0%

Adverse Performance

 

0票 0%

Disdainful Garbage

您所在的用戶組沒(méi)有投票權(quán)限
沙發(fā)
發(fā)表于 2025-3-21 22:30:00 | 只看該作者
板凳
發(fā)表于 2025-3-22 00:46:20 | 只看該作者
地板
發(fā)表于 2025-3-22 05:12:29 | 只看該作者
The Springer International Series in Engineering and Computer Sciencehttp://image.papertrans.cn/s/image/865400.jpg
5#
發(fā)表于 2025-3-22 10:55:34 | 只看該作者
https://doi.org/10.1007/978-1-4615-3646-8Counter; RTL; VLSI; algorithms; computer; computer-aided design (CAD); integrated circuit; logic; manufactur
6#
發(fā)表于 2025-3-22 13:46:55 | 只看該作者
7#
發(fā)表于 2025-3-22 20:42:32 | 只看該作者
Introduction, design tool makes an error (probably due to an undetected bug). . is the process of determining whether the designed circuit is the same as what was specified. ., which is a part of implementation verification, is the process of verifying the equivalence of two logic-level circuits, usually the opt
8#
發(fā)表于 2025-3-22 23:09:51 | 只看該作者
Verification of Sequential Circuits, the design process is sequential logic optimization. At this level, various techniques like retiming [79, 86], decomposition [7], optimization under don’t-cares [38, 80], and re-encoding [38] are used to transform the logic-level description of the circuit to a more optimal description. The focus o
9#
發(fā)表于 2025-3-23 01:46:22 | 只看該作者
Book 1992entation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that ther
10#
發(fā)表于 2025-3-23 07:27:39 | 只看該作者
von 500 Kerzen erhellt sei, giebt für sich allein noch keinen ausreichenden Mafsstab für die Güte der Beleuchtung; im günstigsten Falle würde ein erfahrener Beleuchtungstechniker, welcher die Gr?fse des betreffenden Raumes, die Plazirung der Lampe und ihre Intensit?t mit ?hnlichen anderen F?llen se
 關(guān)于派博傳思  派博傳思旗下網(wǎng)站  友情鏈接
派博傳思介紹 公司地理位置 論文服務(wù)流程 影響因子官網(wǎng) 吾愛(ài)論文網(wǎng) 大講堂 北京大學(xué) Oxford Uni. Harvard Uni.
發(fā)展歷史沿革 期刊點(diǎn)評(píng) 投稿經(jīng)驗(yàn)總結(jié) SCIENCEGARD IMPACTFACTOR 派博系數(shù) 清華大學(xué) Yale Uni. Stanford Uni.
QQ|Archiver|手機(jī)版|小黑屋| 派博傳思國(guó)際 ( 京公網(wǎng)安備110108008328) GMT+8, 2025-10-8 15:20
Copyright © 2001-2015 派博傳思   京公網(wǎng)安備110108008328 版權(quán)所有 All rights reserved
快速回復(fù) 返回頂部 返回列表
黎川县| 南投市| 河源市| 元江| 潮安县| 秦皇岛市| 大渡口区| 响水县| 安福县| 邵阳市| 衡南县| 枝江市| 蒙阴县| 泰安市| 蛟河市| 通许县| 桦川县| 朝阳区| 兴海县| 百色市| 安图县| 定日县| 中山市| 视频| 什邡市| 花垣县| 唐海县| 富顺县| 上栗县| 桑日县| 夏邑县| 临漳县| 绍兴市| 曲靖市| 图们市| 囊谦县| 乌兰县| 玉树县| 盐亭县| 将乐县| 莱州市|