Titlebook: On-Line Testing for VLSI; Michael Nicolaidis,Yervan Zorian,Dhiraj K. Pradan Book 1998 Springer Science+Business Media New York 1998 ASIC.C

Nmda-Receptor

Flirtatious

978-1-4419-5033-8Springer Science+Business Media New York 1998

goodwill

On-Line Testing for VLSI978-1-4757-6069-9Series ISSN 0929-1296

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Efficient Totally Self-Checking Shifter Designd hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths.

Nostalgia

Design of Self-Testing Checkers for ,-out-of-, Codes Using Parallel Countersy Dimakopoulos et al. The checkers are built using a pair of parallel counters (composed of full-adders and half-adders) with a total of . inputs and a 2-rail STC. We show here how to build this type of checkers for a number of ./. codes for which previous methods failed.

樹木中

Instantaneous

Frontiers in Electronic Testinghttp://image.papertrans.cn/o/image/701323.jpg

invulnerable

CLASH

OUTRE