Titlebook: Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip; Pascal Meinerzhagen,Adam Teman,Alexander Fish Book 2018 Springer Internationa

巨頭

Flow Models Studies of Heart Valves,Simulations show successful sub-.. operation for a 2T GC-eDRAM array in 0.18?μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40?nm CMOS can be operated successfully down to the near-.. domain, while simultaneous aggressive technology and voltage scaling to the sub-.. domain are not recommended.

盤旋

Embedded Memories: Introduction,tems, are presented next. Finally, a short review of the state-of-the-art embedded memory technologies, including static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM), is provided, before closing the chapter with a book outline.

sultry

Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain),Simulations show successful sub-.. operation for a 2T GC-eDRAM array in 0.18?μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40?nm CMOS can be operated successfully down to the near-.. domain, while simultaneous aggressive technology and voltage scaling to the sub-.. domain are not recommended.

翻布尋找

宇宙你

Conventional GC-eDRAMs Scaled to Near-Threshold Voltage (NTV),modes, voltage scaling can improve the retention time. Briefly, this chapter shows that a conventional 2T GC bitcell and array organization can be operated at a near-.. voltage (NTV), and that a WBL control scheme during retention modes can improve the retention time under voltage scaling.

波動

prostate-gland

過時

Conclusions,d (sub-..) voltages to power-aware high-performance systems operated at near-threshold (near-..) or nominal supply voltages. It was shown that the key to achieve energy efficiency in GC-eDRAM is a proper understanding and control of the factors that determine the data retention time and its statistical distribution.

動物

要塞