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Titlebook: Emerging Memory Technologies; Design, Architecture Yuan Xie Book 2014 Springer Science+Business Media New York 2014 Emerging Memory.Memory

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發(fā)表于 2025-3-21 18:10:43 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書(shū)目名稱(chēng)Emerging Memory Technologies
副標(biāo)題Design, Architecture
編輯Yuan Xie
視頻videohttp://file.papertrans.cn/309/308308/308308.mp4
概述Provides a comprehensive reference on designing modern circuits with emerging, non-volatile memory technologies, such as MRAM and PCRAM.Explores new design opportunities offered by emerging memory tec
圖書(shū)封面Titlebook: Emerging Memory Technologies; Design, Architecture Yuan Xie Book 2014 Springer Science+Business Media New York 2014 Emerging Memory.Memory
描述This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits.
出版日期Book 2014
關(guān)鍵詞Emerging Memory; Memory Architecture; Memory Circuit Design; Memory Design; NVM SIM; Non-volatile Memory;
版次1
doihttps://doi.org/10.1007/978-1-4419-9551-3
isbn_softcover978-1-4939-4199-5
isbn_ebook978-1-4419-9551-3
copyrightSpringer Science+Business Media New York 2014
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,Hizbullah’s Reconstruction of History,ising NVM for energy efficient computing because of its fast write speed and low-power operations. This chapter provides an overview of the circuit design technologies and applications of resistive memory devices for energy efficient systems, including resistive RAM (ReRAM), nonvolatile logic, and nonvolatile SRAM.
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Introduction: the History of This Book,“0” into an STT-RAM cell is very asymmetric in terms of performance, power, and reliability. In this chapter, we will review this asymmetry and analyze its sources. The impacts of this asymmetry on the STT-RAM cell optimization will be also discussed, followed by the introduction on a model to simulate the STT-RAM cell asymmetry.
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