Titlebook: Die-stacking Architecture; Yuan Xie,Jishen Zhao Book 2015 Springer Nature Switzerland AG 2015

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Mahreen Ameen,Jonathan N.W.N. Barker MDA 3D integrated circuit (3D IC) has two or more active device layers (i.e., CMOS transistor layers) integrated vertically as a single chip, using various integration methods. This chapter will give a brief introduction to different 3D integration technologies, including monolithic 3D ICs and through-silicon-via (TSV)-based 3D ICs.

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Soumya M. Reddy MD,Clifton O. Bingham III MDAs 3D integration technology emerges, the 3D stacking provides great opportunities of improvements in the microarchitecture. In this chapter, we introduce some recent 3D research in the architecture level. These techniques leverage the advantages of 3D and help to improve performance, reduce power consumption, etc.

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3D Integration Technology,A 3D integrated circuit (3D IC) has two or more active device layers (i.e., CMOS transistor layers) integrated vertically as a single chip, using various integration methods. This chapter will give a brief introduction to different 3D integration technologies, including monolithic 3D ICs and through-silicon-via (TSV)-based 3D ICs.

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Benefits of 3D Integration,The following subsections will discuss various architecture design approaches that leverage different benefits that 3D integration technology can offer, namely, wire length reduction, high memory bandwidth, heterogeneous integration, and cost reduction. It will also briefly review 3D network-on-chip architecture designs.

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Fine-granularity 3D Processor Design,As 3D integration technology emerges, the 3D stacking provides great opportunities of improvements in the microarchitecture. In this chapter, we introduce some recent 3D research in the architecture level. These techniques leverage the advantages of 3D and help to improve performance, reduce power consumption, etc.

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Die-stacking Architecture978-3-031-01747-6Series ISSN 1935-3235 Series E-ISSN 1935-3243

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https://doi.org/10.1007/b138733as caches or even on-chip main memories. Different from the research in the previous section, which focuses on optimizations in the fine-granularity (e.g., wire length reduction), the approaches of this section consider the memories as a whole structure and explore the high-level improvements, such as access interfaces, replacement policies, etc.

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