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Titlebook: Designing 2D and 3D Network-on-Chip Architectures; Konstantinos Tatas,Kostas Siozios,Axel Jantsch Book 2014 Springer Science+Business Medi

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發(fā)表于 2025-3-21 16:14:58 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱Designing 2D and 3D Network-on-Chip Architectures
編輯Konstantinos Tatas,Kostas Siozios,Axel Jantsch
視頻videohttp://file.papertrans.cn/269/268896/268896.mp4
概述Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect.Enables readers to exploit parallelism in processor architecture, with interconnect des
圖書封面Titlebook: Designing 2D and 3D Network-on-Chip Architectures;  Konstantinos Tatas,Kostas Siozios,Axel Jantsch Book 2014 Springer Science+Business Medi
描述This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
出版日期Book 2014
關鍵詞3D Network-on-Chip; Embedded Systems Design; Integrated Circuit Design; Low-power Network-on-Chip; Netwo
版次1
doihttps://doi.org/10.1007/978-1-4614-4274-5
isbn_softcover978-1-4939-4550-4
isbn_ebook978-1-4614-4274-5
copyrightSpringer Science+Business Media New York 2014
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On Designing 3-D Platformshe other hand, there are only a few CAD tools for designing 3-D chips (e.g., .Logic [.]). Throughout this chapter we introduce a framework for quantifying the potential gains of employing this new design technology onto digital designs. In contrast to relevant approaches, which are mainly based on m
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發(fā)表于 2025-3-22 04:17:42 | 只看該作者
Ulrich Pfeiffer M. Sc.,Ralph Weidnern modern technologies and explains the classification to transient, intermittent, and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model.
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parallelism in processor architecture, with interconnect desThis book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology
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https://doi.org/10.1007/978-3-642-29800-4tion of routing algorithm and flow control scheme, the router and link design can begin. In this chapter switching techniques, routing algorithms and flow control schemes are discussed and compared, while the design of a generic 2D and 3D router is illustrated and improvements proposed in the literature are discussed.
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