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Titlebook: Defect and Fault Tolerance in VLSI Systems; Volume 2 C. H. Stapper,V. K. Jain,G. Saucier Book 1990 Springer Science+Business Media New York

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書目名稱Defect and Fault Tolerance in VLSI Systems
副標(biāo)題Volume 2
編輯C. H. Stapper,V. K. Jain,G. Saucier
視頻videohttp://file.papertrans.cn/265/264718/264718.mp4
圖書封面Titlebook: Defect and Fault Tolerance in VLSI Systems; Volume 2 C. H. Stapper,V. K. Jain,G. Saucier Book 1990 Springer Science+Business Media New York
描述Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con- tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.
出版日期Book 1990
關(guān)鍵詞RAM; SRAM; VLSI; communication; integrated circuit; logic; programming
版次1
doihttps://doi.org/10.1007/978-1-4757-9957-6
isbn_softcover978-1-4757-9959-0
isbn_ebook978-1-4757-9957-6
copyrightSpringer Science+Business Media New York 1990
The information of publication is updating

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CRT-Pacing Only Versus CRT-DefibrillatorA large number of reconfiguration schemes have been presented for defect tolerant mesh arrays. Here a number of such schemes will be compared. Area and speed based measures are presented, along with a summary of the methods required to estimate area overhead, processor utilization, yield and speed.
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The Effect on Yield of Clustering and Radial Variations in Defect DensityThis work examines the effect on yield, of the clustering and radial variation of fatal defects. An expression is developed for fatal defects as a function of chip area and distance of the chip from the edge of the wafer, and used to estimate the yield of successively larger numbers of array segments of a bipolar SRAM.
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