Titlebook: Computer Engineering and Technology; 16th National Confer Weixia Xu,Liquan Xiao,Chengyi Zhang Conference proceedings 2013 Springer-Verlag B

Anguish

A High Performance DSP System with Fault Tolerant for Space Missionsation methods also be mentioned. In this paper, the system performances are evaluated and analyzed. With running of the correlation function benchmark in this system, it is shown that the system provides high performances under the premise of certified reliability.

Osteons

Admonish

DAMQ Sharing Scheme for Two Physical Channels in High Performance Routerdetailed organization of shared buffer and management of idle buffer. Result of simulation shows that the proposed method has similar performance using only 75% of the buffer size in traditional implementation and outperforms by 5% to 10% in throughput with the same size.

Genteel

Monocle

HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip paper comes up with a new hierarchical routing algorithm——HXY (Hierarchical XY), the simulation results demonstrate the HCCM topology is superior to the Mesh and the Xmesh topology on the performance of system average communication delay and normalized throughput.

平庸的人或物

Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulatoreme based on multicast XY routing algorithm is carried out. The Gem5 Simulator is used to promote the research, experimental results shows our approach have a quite less average packet latency compared with multiple unicast.

Frenetic

Tax Incentives for the Audio Visual Industrypression system is analyzed through experiments. The result shows that the hardware accelerator achieves the function of ROHC packet header compression protocol correctly, and significantly reduces the overhead of packet headers to effectively improve the link utilization; at the same time has good usability and flexibility.

小步走路

expunge

The Design of the ROHC Header Compression Acceleratorpression system is analyzed through experiments. The result shows that the hardware accelerator achieves the function of ROHC packet header compression protocol correctly, and significantly reduces the overhead of packet headers to effectively improve the link utilization; at the same time has good usability and flexibility.

包裹

A Comparison of Folded Architectures for the Discrete Wavelet Transform, filter taps and pipeline insertions have different impacts on the three architectures. Overall, the folded architecture based on lifting structure gives the most desirable figure of merit and the one based on linear systolic array demonstrates the best scalability.