Titlebook: Computer Engineering and Technology; 16th National Confer Weixia Xu,Liquan Xiao,Chengyi Zhang Conference proceedings 2013 Springer-Verlag B

尖

A Configurable Architecture for 1-D Discrete Wavelet Transformf filters with different lengths. The architecture adopts polyphase filter structure and MAC loop based filter (MLBF) to achieve high computing performance and strong generality of the system. Loop unrolling approach is used to eliminate the data hazards caused by pipelining. The hardware usage of t

Graduated

A Comparison of Folded Architectures for the Discrete Wavelet Transform architecture to enhance hardware utilization. This work compares folded architectures for DWT based on three filter structures, the direct form filter, the linear systolic array, and the lifting structure. We generalize the design of these architectures in terms of DWT levels, filter taps and pipel

恩惠

A High Performance DSP System with Fault Tolerant for Space Missions high required on system performance. Conventional techniques mainly focus on the system reliability, at the expense of system performance..In this paper, a flexible, DPS-based, high-performance system is presented. The system could dynamically adapt the system’s level of redundancy according to var

協(xié)迫

Exonerate

A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method word-length optimization model is proposed to find out the optimal word-lengths for signals. Experimental results show that our word-length optimized Fixed-Point generator runs as fast as 403.7 MHz on a Xilinx Virtex-6 FPGA device and is capable of generating 2 samples every clock cycle, which is 1

哀求

DAMQ Sharing Scheme for Two Physical Channels in High Performance Routerorts and channels, but all of which incur significant overheads in hardware costs. In this paper we present a dual-port shared buffer scheme for router. The proposed scheme is based on a dynamically allocated multi queue and four-port Register File. Two physical channels share the same input buffer

Intentional

Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip challenge for NoC(Network-on-Chip). The router is a core element of the NoC, and the virtual channel based on flip-flop which occupies most of the area is the most sensitive element to soft error of the router. Focus on this problem, a dynamic reliable virtual channel architecture is proposed in th

糾纏

HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip structure plays a decisive role on the area and performance of system on chip, and has a profound influence on the transmission capability of system. Based on the distributed routing lookup, we proposed a new kind of inerratic interconnection network is named HCCM (Hierarchical Cross-Connected Mesh

輕快走過

FATAL

1865-0929 ional Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circ