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Titlebook: Circuit and Interconnect Design for RF and High Bit-rate Applications; Hugo Veenstra,John R. Long Book 20081st edition Springer Science+Bu

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書(shū)目名稱Circuit and Interconnect Design for RF and High Bit-rate Applications
編輯Hugo Veenstra,John R. Long
視頻videohttp://file.papertrans.cn/227/226595/226595.mp4
概述Detailed discussion of on-chip interconnect, including theory, design, modelling and evaluation.Extensive Figure-of-Merit analyses for NPN transistors, which results are used for the design of several
叢書(shū)名稱Analog Circuits and Signal Processing
圖書(shū)封面Titlebook: Circuit and Interconnect Design for RF and High Bit-rate Applications;  Hugo Veenstra,John R. Long Book 20081st edition Springer Science+Bu
描述Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the ‘interconnect’) and circuit design. .Circuit and Interconnet Design for RF and High Bit-rate Applications .covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are ‘first-time right’. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also covers single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.
出版日期Book 20081st edition
關(guān)鍵詞Avalanche Multiplication; CMOS; Circuit Design; Cross-Connect Switch; Device Metrics; Distributed Capacit
版次1
doihttps://doi.org/10.1007/978-1-4020-6884-3
isbn_softcover978-90-481-7750-9
isbn_ebook978-1-4020-6884-3Series ISSN 1872-082X Series E-ISSN 2197-1854
issn_series 1872-082X
copyrightSpringer Science+Business Media B.V. 2008
The information of publication is updating

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Aniceto C. Orbeta Jr,Maria Teresa C. Sancheztical networks. The switch matrix, which forms the core of the cross-connect switch IC, is an excellent example showing that optimum performance can only be obtained when circuits and interconnect are optimised together. For the design and optimisation of the signal distribution inside the matrix, e
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International Political Economy Seriestarget is to achieve an output bit-rate of at least 40 Gb/s. Detailed circuit simulations using the SiGe technology also used for the 12.5 Gb/s cross-connect switch described in Chapter 4 revealed that a clock to data delay of approximately 15 ps per latch allows the design of a half-rate PRBS core.
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