Titlebook: Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design; A Self-Test, Self-Di Xiaowei Li,Guihai Yan,Cheng Liu Book

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https://doi.org/10.1007/978-981-19-8551-5Built-in Fault-tolerance; On-chip Fault-tolerance; Self-test, Self-diagnosis, and Self-repair; Fault-to

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erant solution that enables self-test, self-diagnosis and seWith the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built

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onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the imp978-981-19-8553-9978-981-19-8551-5

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Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip DesignA Self-Test, Self-Di

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Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design978-981-19-8551-5

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Wahrscheinlichkeitsverteilungen, Usually, it integrates techniques such as fault detection, fault diagnosis, and fault recovery in chip design such that it can work independently without additional offline testing equipments. In this chapter, we will introduce the background of various silicon faults first and then elaborate the g