| 期刊全稱 | Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design | | 期刊簡稱 | A Self-Test, Self-Di | | 影響因子2023 | Xiaowei Li,Guihai Yan,Cheng Liu | | 視頻video | http://file.papertrans.cn/192/191905/191905.mp4 | | 發(fā)行地址 | Presents a built-in on-chip fault-tolerant computing paradigm that can be applied to a variety of VLSI designs.Provides a holistic fault-tolerant solution that enables self-test, self-diagnosis and se | | 圖書封面 |  | | 影響因子 | With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the imp | | Pindex | Book 2023 |
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