Titlebook: Architecture of Computing Systems -- ARCS 2013; 26th International C Hana Kubátová,Christian Hochberger,Bernhard Sick Conference proceeding

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書目名稱Architecture of Computing Systems -- ARCS 2013影響因子(影響力)




書目名稱Architecture of Computing Systems -- ARCS 2013影響因子(影響力)學(xué)科排名




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書目名稱Architecture of Computing Systems -- ARCS 2013年度引用學(xué)科排名




書目名稱Architecture of Computing Systems -- ARCS 2013讀者反饋




書目名稱Architecture of Computing Systems -- ARCS 2013讀者反饋學(xué)科排名

Sleep-Paralysis

Power Monitoring for Mixed-Criticality on a Many-Core Platform,dence in terms of time and space, but also in terms of power consumption as the available energy for a many-core system has to be shared by all running applications. Increased power consumption of one application may reduce the available energy for other applications or the reliability and lifetime

mydriatic

On Confident Task-Accurate Performance Estimation,ate performance by simulating task-level models annotated with nominal execution time. In early design phases, source code, which is necessary for generating accurate annotations, is usually not available. Instead, extrapolated values or even estimated values are used for performance estimation, whi

先驅(qū)

Fecundity

定點(diǎn)

A Multi-core Memory Organization for 3-D DRAM as Main Memory,s and reduce energy consumption in multicore systems. These new memory technologies present both opportunities and challenges to computer systems design..In this paper we address how such memories should be organized to fully benefit from these technologies. We propose to keep 3-D DRAMs as main memo

cruise

山羊

Virtual Register Renaming, a reorder buffer or physical registers for register renaming and instruction retirement. Instead, it uses a large number of virtual register IDs for register renaming, a physical register file of the same size as the logical register file, and checkpoints to bulk retire instructions and to recover

有偏見

Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Causfrom both timing disturbances and interrupt overloads is presented. It is supposed that the software is driven by a real-time operating system and that the software is critical, so it is expected not to fail. The architecture is composed of an FPGA (MCU) utilized to run the hardware (software) part

galley