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Titlebook: Algorithms for VLSI Physical Design Automation; Naveed Sherwani Book 1995Latest edition Springer Science+Business Media New York 1995 Fiel

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期刊全稱Algorithms for VLSI Physical Design Automation
影響因子2023Naveed Sherwani
視頻videohttp://file.papertrans.cn/154/153254/153254.mp4
圖書(shū)封面Titlebook: Algorithms for VLSI Physical Design Automation;  Naveed Sherwani Book 1995Latest edition Springer Science+Business Media New York 1995 Fiel
影響因子.Algorithms for VLSI Physical Design Automation, SecondEdition. is a core reference text for graduate students and CADprofessionals. Based on the very successful First Edition, it providesa comprehensive treatment of the principles and algorithms of VLSIphysical design, presenting the concepts and algorithms in anintuitive manner. Each chapter contains 3-4 algorithms that arediscussed in detail. Additional algorithms are presented in a somewhatshorter format. References to advanced algorithms are presented at theend of each chapter. ..Algorithms for VLSI Physical Design Automation. covers allaspects of physical design. In 1992, when the First Edition waspublished, the largest available microprocessor had one milliontransistors and was fabricated using three metal layers. Now weprocess with six metal layers, fabricating 15 million transistors on achip. Designs are moving to the 500-700 MHz frequency goal.These stunning developments have significantly altered the VLSI field:over-the-cell routing and early floorplanning have come to occupy acentral place in the physical design flow. .This Second Edition introduces a .realistic. picture to thereader, exposing the concerns facing the VL
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Physical Design Automation of MCMs,th the MCM designs. Let us just consider the problem of routing in MCM. The signal effects of long lines in terms of crosstalk, noise, and reflections must be taken into account during routing. In addition, as high speeds are explored, the transmission line behavior of the interconnect must be model
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Urs Büttner,Corinna Norrick-Rühlhe fab for fabrication. Symbolic database captures net and transistor attributes. It allows a designer to rapidly navigate throughout the database and make quick edits while working at a higher level. The symbolic database is converted into a polygon database prior to tapeout. In the polygon databas
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Urs Büttner,Corinna Norrick-Rühlermine the overall yield of the fabrication process. The key factor which describes the fab in terms of technology is minimum feature size it is capable of manufacturing. For example, a fab which runs a 0.35 micron fabrication process is simply referred to as a 0.35 micron fab.
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https://doi.org/10.1007/978-3-658-41633-1ces has led to a significant increase in number of interconnections. Interconnect delays, which were considered to be insignificant earlier, have now become comparable, if not more prominent than the gate delays.
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