Titlebook: VLSI for Embedded Intelligence; Proceedings of the 2 Anu Gupta,Jai Gopal Pandey,Devesh Dwivedi Conference proceedings 2025 The Editor(s) (i

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Optimized Composite Field-Based Hardware Architectures for AES S-Box Using Logic Decomposition Techf our proposed designs has a reduction of around 18% in the number of slices and nearly 50% in power consumption compared with the state-of-the-art architectures for the FPGA platform. Again, for standard cell libraries, our proposed design exhibits a delay reduction of around 41%, making them useful for resource-constrained applications.

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