| 書目名稱 | Verification Methodology Manual for SystemVerilog | | 編輯 | Janick Bergeron,Eduard Cerny,Andrew Nightingale | | 視頻video | http://file.papertrans.cn/982/981691/981691.mp4 | | 概述 | New IEEE SystemVerilog standard explained.Covers the combination of methodology and SystemVerilog.Includes supplementary material: | | 圖書封面 |  | | 描述 | .Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies. ..Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform...Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. T | | 出版日期 | Book 2006 | | 關(guān)鍵詞 | Assertion-based verification; Description language; Functional verification; SystemVerilog; Test benches | | 版次 | 1 | | doi | https://doi.org/10.1007/b135575 | | isbn_softcover | 978-1-4614-9813-1 | | isbn_ebook | 978-0-387-25556-9 | | copyright | Springer-Verlag US 2006 |
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