Titlebook: Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits; Martin Wirnshofer Book 2013 Springer Science+Business Media Dordrecht

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Sources of Variation,tuations affect the switching speed of the transistors and thus the timing of the logic. To guarantee fault-free operation for a specified clock frequency, IC designers have to quantify these uncertainties and account for them adequately. This is typically done by guard-banding, i.e. adding sufficie

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Related Work,. To cope with these uncertainties, worst-case guard-banding is still the most common design approach. As the worst-case is very rare however, in most cases power or performance is wasted by this approach..By scaling the operating voltage, energy efficiency can be increased. Tuning the supply voltag

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Adaptive Voltage Scaling by In-situ Delay Monitoring,ous data transitions in critical paths. Late data transitions are defined by the pre-error detection window, i.e. a defined time interval .. before the triggering edge of the clock..The timing of digital circuits is influenced by PVTA variations and so is the frequency of pre-errors. The pre-error r

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Modeling the AVS Control Loop, (Pre-Error flip-flops) acting as sensors of this system. The following chapter will now deal with the entire control loop. First, we show how the whole system can be analyzed accurately and at the same time efficiently. Subsequently, the Markov chain, which is used to model the AVS system, is expla

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Conclusion,increasing PVT variations as well as aging effects in integrated circuits. This Pre-Error AVS approach reduces unnecessary voltage safety margin by adapting the supply voltage to the actual operating condition of a chip and thereby optimizes power consumption.