Titlebook: VLSI: Integrated Systems on Silicon; IFIP TC10 WG10.5 Int Ricardo Reis,Luc Claesen Book 1997 IFIP International Federation for Information

華而不實

Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluationore profitable. This minimum value depends on cache size, block size, the access time of the cache and the miss penalty time. For computing the access time of the caches, an analytical access time model for on-chip caches already proposed in the open literature has been used.

吼叫

Perineum

A set of device generators for analogue and mixed-signal layout synthesiss. The context and the objectives of this work, the development strategy and the main functionalities are presented. Finally, an example is given. These generators have been successfully used to design several circuits.

AMITY

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computingption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in the die area of 7.66 .. by means of a 0.35. CMOS technology, with the dissipation of 146.60 mW from a single 3.3V supply.

白楊

VLSI Implementation of Contour Extraction from Real Time Image Sequencesjective is to determine whether or not the neighborhood central pixel belongs to a continuous boundary line passing across the window. Test results show that one-pixel wide continuous boundary lines can be extracted using this algorithm.

Palatial

On-line testing of analog circuits by adaptive filtersing methodology and experimental results showing easy detection of soft, large-deviation and hard faults, with a low cost digital processor. Components variations as low as 10% have been detected, as the comparison parameter (output error power) varied from 300% to 20%.

永久

A Low-Voltage Operational Transconductance Amplifier and Its Application to a Bandpass Gm-C Filter — suitable for high frequency operation. With this OTA, a prototype bandpass Gm-C filter was implemented in 0.8μm CMOS process. The center frequency can be controlled from 15.0MHz to 33.0MHz. The filter consumes only 0.43mW per pole when the center frequency is 15.0MHz.

在前面

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computingticability for mobile computing has been extremely explored by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in t

油氈

A VLSI architecture for real-time edge linkingce thin edges with discontinuities. In this paper, a real-time algorithm and its VLSI implementation for linking broken edges is presented. First, all broken edge points inside a 12×12 moving window are identified. The 12×12 window scans the input gray level edge map converting it into three levels

Ingrained

VLSI Implementation of Contour Extraction from Real Time Image Sequencesworks on the gradient image and uses a set of primitive paths to generate all possible contour paths on a neighborhood defined by a 5×5 window. The objective is to determine whether or not the neighborhood central pixel belongs to a continuous boundary line passing across the window. Test results sh