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Titlebook: VLSI-SoC: Technology Advancement on SoC Design; 29th IFIP WG 10.5/IE Victor Grimblatt,Chip Hong Chang,Andrea Calimera Conference proceeding

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樓主: Hypothesis
41#
發(fā)表于 2025-3-28 18:17:08 | 只看該作者
42#
發(fā)表于 2025-3-28 20:11:42 | 只看該作者
,On the?Efficiency of?AdapTTA: An Adaptive Test-Time Augmentation Strategy for?Reliable Embedded ConTA addresses a limitation inherent to any deep learning pipeline, that is, training datasets cover only a tiny portion of the possible inputs. For this reason, when ported to real-life scenarios, ConvNets may suffer from substantial accuracy loss due to unseen input patterns received under unpredict
43#
發(fā)表于 2025-3-29 02:08:14 | 只看該作者
,Low-Overhead Early-Stopping Policies for?Efficient Random Forests Inference on?Microcontrollers,. Large RFs however, still have significant energy costs, a serious concern for battery-operated ultra-low-power devices. Following the adaptive (or dynamic) inference paradigm, we introduce a hardware-friendly early stopping policy for RF-based classifiers, halting the execution as soon as a suffic
44#
發(fā)表于 2025-3-29 06:04:35 | 只看該作者
,Transformative Hardware Design Following the?Model-Driven Architecture Vision, satisfy emerging aspectual design requirements such as on-chip debug and functional safety. These code modifications escalate development, verification efforts, and deteriorate code reuse. This paper proposes a highly efficient transformative hardware design methodology that leverages graph-grammar
45#
發(fā)表于 2025-3-29 10:03:31 | 只看該作者
,Exploiting Program Slicing and?Instruction Clusterization to?Identify the?Cause of?Faulty Temporal the bug is found, further effort must be spent by the design team to understand its cause and then fix the originating error. This requires a tedious and time-consuming process, generally based on the manual inspection of the execution traces of the design under verification (DUV). This process beco
46#
發(fā)表于 2025-3-29 14:48:00 | 只看該作者
,A DfT Strategy for?Detecting Emerging Faults in?RRAMs,ng high computing and storage capabilities pose significant challenges to device technologies and computer architectures. From the point of view of device technology, memristive devices have become the most promising candidate to complement and/or replace CMOS technology. The key advantages are the
47#
發(fā)表于 2025-3-29 17:13:04 | 只看該作者
FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models,safety analysis (e.g., Failure Mode and Effects Analysis) is often only relying on human experience and therefore lacks detailed data. Performing more detailed analyses on complex systems is a major challenge to avoid pessimistic assumptions and consequently to avoid over-design of the system, i.e.,
48#
發(fā)表于 2025-3-29 23:46:27 | 只看該作者
Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs,s applied in automotive and aerospace applications to increase their overall resiliency against SEEs. The current SEE resilient SRAM modules are obtained by applying radiation-hardened by design solutions which leads to elevated area overhead and difficulty to tune the resiliency capability with res
49#
發(fā)表于 2025-3-30 03:48:04 | 只看該作者
Design of a Reconfigurable Optical Computing Architecture Using Phase Change Material,ed systems. Micrometer-scale optical devices call for reconfigurable architectures to maximize resources utilization. Typical reconfigurable optical computing architectures involve micro-ring resonators for electro-optic modulation. However, such devices require voltage and thermal tuning to compens
50#
發(fā)表于 2025-3-30 04:02:55 | 只看該作者
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