Titlebook: VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things; 25th IFIP WG 10.5/IE Michail Maniatakos,Ibrahim (Abe) M. Elfadel,Rica

neolith

Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs,nalysis of static and dynamic fault behavior for FinFET-based SRAMs is described. The proposed analysis has been performed through SPICE simulations, adopting a compact Predictive Technology Model (PTM) of FinFET transistors, considering different technological nodes. Faults have been categorized as single or coupling, static or dynamic.

俗艷

Constant

FUSE

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI,es at VDDL?=?0.6?V and VDDH?=?1.2?V under 2?V pMOS RBB while suppressing the static dc current in the VDDH domain. We also demonstrate that adaptive RBB control for pMOS can maintain effectiveness of this approach under process and temperature variations.

勾引

污穢

Disk199

ICLE

A Wearable Neuro-Degenerative Diseases Classification System Using Human Gait Dynamics,d. NDDs are chronic diseases that affect the human central nervous system causing loss of neurons within the brain and/or spinal cord. This causes deterioration in movement and mental functioning of the patients. The current medications for this group of disorders are limited and aim to treat the sy

CAB

Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applicationg power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A common approach is to generate a POR signal by comparing the supply voltage with a reference voltage. Pseudo dual/two port memories are used in graphic applications where parallel computing is prime fact

TERRA