Titlebook: VLSI-SoC: New Technology Enabler; 27th IFIP WG 10.5/IE Carolina Metzler,Pierre-Emmanuel Gaillardon,Ricard Conference proceedings 2020 IFIP

取回

Hardware-Enabled Secure Firmware Updates in Embedded Systems,firmware updates, manufacturers and firmware developers often consider firmware security as a secondary task. As a result, firmware often turns into an alluring target for adversaries to inject malicious code into embedded devices. In this work, we present a framework that supports secure and fast f

Gesture

共同確定為確

Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs, NoCs (PP-NoCs), a widely used real-time on-chip interconnection structure that offers communication predictability. A deep analysis of the PP-NoC parameters and their impact on system security is required. Moreover, countermeasures that can protect the system while guaranteeing the real-time capabi

艱苦地移動

Offset-Compensation Systems for Multi-Gbit/s Optical Receivers,ter. The analytical expression for the highest lower-cut-off frequency of the OC with minimum impact on the sensitivity is found. Existing OC solutions are discussed. Then, a novel mixed-signal (MS) architecture is introduced which uses digital filtering of the signal, and current-digital-to-analog

隱語

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing, requirements by representing the operands using only one bit. Also, due to 90% of the operations executed by CNNs and BNNs being convolutions, a quest for custom accelerators to optimize the convolution operation and reduce data movements has started, in which . (RRAM)-based accelerators have prove

煩憂

Semi- and Fully-Random Access LUTs for Smooth Functions,cant area penalty. If the function is smooth, MultiPartite table method (MP) can circumvent the area problem by breaking up the implementation into multiple smaller LUTs. However, even some of these smaller LUTs may be big in high accuracy MP implementations. Lossless LUT compression can be applied

evasive

A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors,ontrol of the device polarity and dual-threshold voltage characteristics. These operations can be used to reduce the number of transistors required for logic implementation resulting in compact logic designs and reductions in chip area and leakage current..However, the evaluation of TIGFET-based des

夾死提手勢

Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework, object detection and image recognition based on convolutional neural networks are accelerated by offloading these computation-intensive algorithms to the accelerators to meet their stringent performance constraints. Conventionally there are device-specific runtime and programming languages supporte

Mundane

Conference proceedings 2020ale Integration, VLSI-SoC 2019, held in Cusco, Peru, in October 2019...The 15 full papers included in this volume were carefully reviewed and selected from the 28 papers (out of 82 submissions) presented at the conference. The papers discuss the latest academic and industrial results and development

habile

1868-4238 ing manufacturing technologies. In particular they address cutting-edge research fields like heterogeneous, neuromorphic and brain-inspired, biologically-inspired, approximate computing systems..978-3-030-53275-8978-3-030-53273-4Series ISSN 1868-4238 Series E-ISSN 1868-422X