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Titlebook: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; 20th IFIP WG 10.5/IE Andreas Burg,Ay?e Co?kun,Ricardo Reis Conference proc

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發(fā)表于 2025-3-21 16:31:44 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
副標題20th IFIP WG 10.5/IE
編輯Andreas Burg,Ay?e Co?kun,Ricardo Reis
視頻videohttp://file.papertrans.cn/981/980125/980125.mp4
概述State-of-the-art research.Up-to-date results.Unique visibility
叢書名稱IFIP Advances in Information and Communication Technology
圖書封面Titlebook: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; 20th IFIP WG 10.5/IE Andreas Burg,Ay?e Co?kun,Ricardo Reis Conference proc
描述This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.
出版日期Conference proceedings 2013
關鍵詞adaptive routing; multi-core processor; network-on-chip; smart memory; threshold gates
版次1
doihttps://doi.org/10.1007/978-3-642-45073-0
isbn_softcover978-3-662-52529-6
isbn_ebook978-3-642-45073-0Series ISSN 1868-4238 Series E-ISSN 1868-422X
issn_series 1868-4238
copyrightIFIP International Federation for Information Processing 2013
The information of publication is updating

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Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnectionsthe number of faulty interconnections. Results for MPEG4 and VOPD applications running on the NoC with different faulty case-study scenarios show that the proposed techniques can tolerate many faulty interconnections with a low area, performance and power overheads.
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