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Titlebook: VLSI Physical Design: From Graph Partitioning to Timing Closure; Andrew B. Kahng,Jens Lienig,Jin Hu Textbook 20111st edition Springer Scie

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發(fā)表于 2025-3-21 17:59:39 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱VLSI Physical Design: From Graph Partitioning to Timing Closure
編輯Andrew B. Kahng,Jens Lienig,Jin Hu
視頻videohttp://file.papertrans.cn/981/980097/980097.mp4
概述Comprehensive coverage of physical design of integrated circuits, PCBs and MCMs, with emphasis on practical algorithms and methodologies.A chapter on timing closure that includes a discussion of desig
圖書封面Titlebook: VLSI Physical Design: From Graph Partitioning to Timing Closure;  Andrew B. Kahng,Jens Lienig,Jin Hu Textbook 20111st edition Springer Scie
描述.Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact...?.."VLSI Physical Design: From Graph Partitioning to Timing Closure" .introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure..? ? ? ? ? ? ? ? ? ??.? ?.
出版日期Textbook 20111st edition
關鍵詞EDA; Electronic Design Automation; Electronics; Physical design algorithms; VLSI design; chip planning; de
版次1
doihttps://doi.org/10.1007/978-90-481-9591-6
isbn_softcover978-94-007-9020-9
isbn_ebook978-90-481-9591-6
copyrightSpringer Science+Business Media B.V. 2011
The information of publication is updating

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沙發(fā)
發(fā)表于 2025-3-21 23:30:30 | 只看該作者
Specialized Routing,1–7.2) directly constructs metal routes for signal connections. Unlike routing with multiple metal layers, area routing emphasizes crossing minimization. Non-Manhattan routing is discussed in Sec. 7.3, and nets that require special treatment, such as clock signals, are discussed in Secs. 7.4–7.5.
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Introduction,ly performed by specialized software, which is frequently updated to reflect improvements in semiconductor technologies and increasing design complexities. A . of this software needs a high-level understanding of the implemented algorithms. On the other hand, a . of this software must have a strong
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Netlist and System Partitioning, tasks increasingly difficult. A common strategy is to . or divide the design into smaller portions, each of which can be processed with some degree of independence and parallelism. A . strategy for chip design can be implemented by laying out each block individually and reassembling the results as
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Global and Detailed Placement,he locations of standard cells or logic elements within each block while addressing optimization objectives, e.g., minimizing the total length of connections between elements. Specifically, . (Sec. 4.3) assigns general locations to movable objects, while . (Sec. 4.4) refines object locations to lega
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Specialized Routing, of designs, such as analog circuits and printed circuit boards (PCBs) with gridless (trackless) routing, do not warrant this distinction. Smaller, older designs with only one or two metal layers also fall into this category. When global and detailed routing are not performed separately, . (Secs. 7.
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Textbook 20111st edition prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level
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