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Titlebook: VLSI CAD Tools and Applications; Wolfgang Fichtner,Martin Morf Book 1987 Kluwer Academic Publishers 1987 VLSI.algorithms.computer-aided de

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樓主: cerebellum
51#
發(fā)表于 2025-3-30 11:30:33 | 只看該作者
A Comparison of Microprocessor Architectures in View of Code Generation by a Compiler,hould therefore be carefully tuned for optimal effectiveness. Otherwise, compromises between more complex compiling algorithms and less efficient compiled code are inevitable. We investigate three processor architectures and analyze their effectiveness for use with a high-level language. The conclus
52#
發(fā)表于 2025-3-30 14:23:16 | 只看該作者
Fault Tolerant VLSI Multicomputers,em consists of computation nodes and communication nodes, interconnected by high-speed dedicated links. These components are relied upon to detect errors while system level protocols are used for error recovery and reconfiguration. The use of duplication and matching for implementing the self-checki
53#
發(fā)表于 2025-3-30 19:37:27 | 只看該作者
The VLSI Design Automation Assistant: An IBM System/370 Design,ths and control signals from an algorithmic description of a VLSI system. This chapter shows the generality of design knowledge in the DAA by comparing and contrasting an IBM System/370 designed by an expert human designer, Claud Davis, against the design produced by the DAA. For each difference, po
54#
發(fā)表于 2025-3-30 23:57:09 | 只看該作者
Higher Level Simulation and CHDLs,It first gives a survey on objectives of its use in simulation. Then it briefly introduces a subset of a modern register transfer language (RT language). Finally it gives a survey on various CHDL-based CAD tools and its linkage to physical design, as well as its integration into CAD environments.
55#
發(fā)表于 2025-3-31 01:28:46 | 只看該作者
VLSI Testing: DFT Strategies and CAD Tools,s is due to the higher number of gates which is not matched by an adequate increase in pin count. Using CAD tools, the cost of designing such “more complicated chips” can of course be kept within reasonable limits, but the cost of test preparation will explode due to the level of complexity. Another
56#
發(fā)表于 2025-3-31 05:56:24 | 只看該作者
57#
發(fā)表于 2025-3-31 11:54:36 | 只看該作者
58#
發(fā)表于 2025-3-31 13:37:18 | 只看該作者
59#
發(fā)表于 2025-3-31 17:41:30 | 只看該作者
60#
發(fā)表于 2025-4-1 00:53:26 | 只看該作者
CAD Tools for Mask Generation,the context of the symbolic design environment. General overviews are not given in most cases. Instead, a feel for this technology is given through specific examples of a system most familiar to the author.
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