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Titlebook: Understanding Behavioral Synthesis; A Practical Guide to John P. Elliott Book 1999 Springer Science+Business Media New York 1999 ASIC.FPGA.

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發(fā)表于 2025-3-21 19:23:50 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱Understanding Behavioral Synthesis
副標題A Practical Guide to
編輯John P. Elliott
視頻videohttp://file.papertrans.cn/942/941318/941318.mp4
圖書封面Titlebook: Understanding Behavioral Synthesis; A Practical Guide to John P. Elliott Book 1999 Springer Science+Business Media New York 1999 ASIC.FPGA.
描述.Behavioral Synthesis: A Practical Guide to High-LevelDesign. includes details on new material and new interpretations ofold material with an emphasis on practical information. The intendedaudience is the ASIC (or high-end FPGA) designer who will be usingbehavioral synthesis, the manager who will be working with thosedesigners, or the engineering student who is studying leading-edgedesign techniques. .Today‘s designs are creating tremendous pressures for digitaldesigners. Not only must they compress more functionality onto asingle IC, but this has to be done on shorter schedules to stay aheadin extremely competitive markets. To meet these opposing demands,designers must work at a new, higher level of abstraction toefficiently make the kind of architectural decisions that are criticalto the success of today‘s complex designs. In other words, they mustinclude behavioral design in their flow. .The biggest challenge to adopting behavioral design is changing themindset of the designer. Instead of describing system functionality ingreat detail, the designer outlines the design in broader, moreabstract terms. The ability to easily and efficiently considermultiple design alternatives over
出版日期Book 1999
關鍵詞ASIC; FPGA; Field Programmable Gate Array; Filter; ROM; architecture; integrated circuit
版次1
doihttps://doi.org/10.1007/978-1-4615-5059-4
isbn_softcover978-1-4613-7300-1
isbn_ebook978-1-4615-5059-4
copyrightSpringer Science+Business Media New York 1999
The information of publication is updating

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板凳
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地板
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How Did We Get Here?,To understand the development of behavioral synthesis, take a step back in time and relive some of the EDA tool decisions that designers have made in the past. Put yourself in the position of the typical designer and walk through this bit of history.
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發(fā)表于 2025-3-22 09:45:40 | 只看該作者
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The Behavioral Synthesis Process,This chapter discusses the steps performed during behavioral synthesis. While this chapter discusses some topics that are not essential to the . of behavioral synthesis tools, a good understanding of these steps will provide insight into the results produced by behavioral synthesis.
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發(fā)表于 2025-3-22 19:16:51 | 只看該作者
Data Types,A number of different data types can be expressed using the VHDL language. A designer must understand which data types are supported by behavioral synthesis and how those data types are translated into a gate-level netlist.
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發(fā)表于 2025-3-22 21:54:01 | 只看該作者
Entities, Architectures, and Processes,In VHDL, the interface for a design is specified by the ENTITY declaration.
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Pipelining,Behavioral synthesis tools support pipelining techniques to improve the throughput of synthesized designs.
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