| 書目名稱 | The Verilog PLI Handbook | | 副標(biāo)題 | A User’s Guide and C | | 編輯 | Stuart Sutherland | | 視頻video | http://file.papertrans.cn/922/921989/921989.mp4 | | 圖書封面 |  | | 描述 | .The Verilog Programming Language Interface, commonly called the Verilog PU, is one of the more powerful features of Verilog. The PU provides a means for both hardware designers and software engineers to interface their own programs to commercial Verilog simulators. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired. Just a few of the common uses of the PU include interfacing Veri log simulations to C language models, adding custom graphical tools to a simulator, reading and writing proprietary file formats from within a simulation, performing test coverage analysis during simulation, and so forth. The applications possible with the Verilog PLI are endless. .Intended audience: this book is written for digital design engineers with a background in the Verilog Hardware Description Language and a fundamental knowledge of the C programming language. It is expected that thereader: .Has a basic knowledge of hardware engineering, specifically digital design of ASIC and FPGA technologies..Is familiar with the Verilog Hardware Description Language (HDL), and can write models of hardware circuits in Verilog, can write simulation te | | 出版日期 | Book 1999 | | 關(guān)鍵詞 | Hardware; Interface; Verilog; programming; simulation | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-5017-4 | | isbn_softcover | 978-1-4613-7279-0 | | isbn_ebook | 978-1-4615-5017-4 | | copyright | Springer Science+Business Media New York 1999 |
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