| 書(shū)目名稱 | The Architecture of High Performance Computers | | 編輯 | Roland N. Ibbett | | 視頻video | http://file.papertrans.cn/905/904512/904512.mp4 | | 圖書(shū)封面 |  | | 描述 | Introduction 1. 1 Historical Developments 1 1. 2 Techniques for Improving Performance 2 1. 3 An Architectural Design Example 3 2 Instructions and Addresses 2. 1 Three-address Systems - The CDC 6600 and 7600 7 2. 2 Two-address Systems - The IBM System/360 and /370 10 2. 3 One-address Systems 12 2. 4 Zero-address Systems 15 2. 5 The MU5 Instruction Set 17 2. 6 Comparing Instruction Formats 22 3 Storage Hierarcbies 3. 1 Store Interleaving 26 3. 2 The Atlas Paging System 29 3. 3 IBM Cache Systems 33 3. 4 The MU5 Name Store 37 3. 5 Data Transfers in the MU5 Storage Hierarchy 44 4 Pipelines 4. 1 The MU5 Primary Operand Unit Pipeline 49 4. 2 Arithmetic Pipelines - The TI ASC 62 4. 3 The IBM System/360 Model 91 Common Data Bus 67 5 Instruction Buffering 5. 1 The IBM System/360 Model 195 Instruction Processor 72 5. 2 Instruction Buffering in CDC Computers 77 5. 3 The MU5 Instruction Buffer Unit 82 5. 4 The CRAY-1 Instruction Buffers 87 5. 5 Position of the Control Point 89 6 Parallel Functional Units 6. 1 The CDC 6600 Central Processor 95 6. 2 The CDC 7600 Central Processor 104 6. 3 Performance 110 6 ? 4 The CRA Y-1 112 7 Vector Processors 7. 1 Vector Facilities in MU5 126 7. 2 String Opera | | 出版日期 | Book 1982 | | 關(guān)鍵詞 | System/36; arithmetic; computer; control; design; development; form; function; functional; model; performance; | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4757-6715-5 | | isbn_softcover | 978-1-4757-6717-9 | | isbn_ebook | 978-1-4757-6715-5 | | copyright | Roland N. Ibbett 1982 |
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