| 書(shū)目名稱(chēng) | Testing and Reliable Design of CMOS Circuits |
| 編輯 | Niraj K. Jha,Sandip Kundu |
| 視頻video | http://file.papertrans.cn/904/903413/903413.mp4 |
| 叢書(shū)名稱(chēng) | The Springer International Series in Engineering and Computer Science |
| 圖書(shū)封面 |  |
| 描述 | In the last few years CMOS technology has become increas- ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den- sity and low power requirement. The ability to realize very com- plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance- ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor- tance of CMOS technology, |
| 出版日期 | Book 1990 |
| 關(guān)鍵詞 | CMOS; VLSI; algorithms; circuit; complexity; computer; design; digital system; electronics; logic; model; netwo |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4613-1525-4 |
| isbn_softcover | 978-1-4612-8818-3 |
| isbn_ebook | 978-1-4613-1525-4Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Kluwer Academic Publishers 1990 |
|Archiver|手機(jī)版|小黑屋|
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