Titlebook: SOC Design Methodologies; IFIP TC10 / WG10.5 E Michel Robert,Bruno Rouzeyre,Marie-Lise Flottes Book 2002 IFIP International Federation for

生命

A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminalsr flexibility and performances. In order to define a system that combines high-performance and low-energy consumption, a dynamically reconfigurable architecture, designed with energy awareness is proposed. This paper presents the main features of the DART architecture along with results from the app

Terrace

MOAN

Reconfigurable Architecture Using High Speed FPGA the fly) by scheduling the execution of different algorithms building an application. Our project joins the efforts of ten laboratories working on methods and tools for Adequation Algorithm Architecture. The design of a hardware template with such a concept, will help the emergence of new methods f

AXIS

A簡(jiǎn)潔的

Distributed Collaborative Design over Cave2 Frameworkimplemented over the software infrastructure developed under the Cave Project, taking advantage on both definitions of the framework concept: classical electronic design frameworks and object-oriented extensible data modeling. The final result is a design environment accessible over Internet-like ne

mettlesome

High Performance Java Hardware Engine and Software Kernel for Embedded Systems devised for existing embedded systems in order to execute Java applications efficiently, in such a way that 39 instructions are added to the original JVM dedicatedly for the software kernel implementation. The whole embedded system including the hardware engine of 6-stage pipeline with 30K gates ca

dandruff

Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Softwges, specially the hardware description languages lack constructs that allow the IP designer to develop highly re-usable IP blocks. In this paper is described an abstract communication mechanism that uses extensions to the VHDL language, communication library for software and automatic interface gen

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An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms obtain the Pareto-optimal set of configurations that provide multi-criteria optimisation. The paper proposes a methodology based on evolutionary techniques for exploration of the range of possible configurations of a parameterized system [1]. A highly parametric system-on-a-chip for digital camera

explicit

Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 ,m Bulk and Silicon-On-Insulator CMOt from the full potential of the design style and to be able to port it to different technologies, it is important to take into account the specific features of each technology. We investigate the case of three advanced 0.25 .m CMOS technologies: bulk, Partially-Depleted SOI and Fully-Depleted SOI.

蛙鳴聲

A Standardized Co-simulation Backboneanslation are some of the main challenges. This paper discusses the advantages of the HLA (High Level Architecture) standard to solve these problems and presents a generic architecture to support environments for geographically distributed co-simulation, called Distributed Co-simulation Backbone (DC