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Titlebook: Reversible Computation; Third International Alexis Vos,Robert Wille Conference proceedings 2012 Springer-Verlag Berlin Heidelberg 2012 log

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樓主: Lactase
11#
發(fā)表于 2025-3-23 11:06:17 | 只看該作者
Towards a Reversible Functional Language, injectivity along with local backward determinism, an important operational property for an efficient reversible language. We define a concise reversible first-order functional language in which access to the backward semantics is provided to the programmer by inverse function calls. Reversibility
12#
發(fā)表于 2025-3-23 14:08:33 | 只看該作者
13#
發(fā)表于 2025-3-23 19:54:26 | 只看該作者
14#
發(fā)表于 2025-3-23 22:19:34 | 只看該作者
15#
發(fā)表于 2025-3-24 05:54:29 | 只看該作者
Transforming MCT Circuits to NCVW Circuits,. The library containing NOT, controlled-NOT and controlled square-root-of-NOT gates has been considered extensively. In this paper, we extend the library to include fourth-root-of-NOT gates. Experimental results using REVLIB benchmark circuits show that using this extended library results in smalle
16#
發(fā)表于 2025-3-24 10:06:41 | 只看該作者
Changing the Gate Order for Optimal LNN Conversion,tion processing should have intrinsic limitations; physically realizable operations would be only interaction between neighbor qubits. To use only such physically realizable operations, we need to convert a general quantum circuit into one for an so-called Linear Nearest Neighbor (LNN) architecture
17#
發(fā)表于 2025-3-24 11:49:07 | 只看該作者
Towards the Limits of Cascaded Reversible (Quantum-Inspired) Circuits,hat . may be used for reversible linear computations. In order for this new technology to be used in commercial applications, several questions have to be answerd first. In particular, the number of gates possibly cascaded, the maximum reachable frequency, the maximum acceptable delays and amplitude
18#
發(fā)表于 2025-3-24 18:32:22 | 只看該作者
Interfacing Reversible Pass-Transistor CMOS Chips with Conventional Restoring CMOS Circuits,ation. This, however, raises new issues regarding the compatibility between this adiabatic logic implementation and conventional CMOS logic. The greatest difficulty is brought by the difference in signal shape used by these two logic families. Whereas standard switching CMOS circuits are operated by
19#
發(fā)表于 2025-3-24 20:50:49 | 只看該作者
20#
發(fā)表于 2025-3-25 00:30:41 | 只看該作者
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