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Titlebook: Reuse Techniques for VLSI Design; Ralf Seepold,Arno Kunzmann Book 1999 Springer Science+Business Media Dordrecht 1999 ASIC.SoC.Usability.V

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書(shū)目名稱(chēng)Reuse Techniques for VLSI Design
編輯Ralf Seepold,Arno Kunzmann
視頻videohttp://file.papertrans.cn/830/829344/829344.mp4
圖書(shū)封面Titlebook: Reuse Techniques for VLSI Design;  Ralf Seepold,Arno Kunzmann Book 1999 Springer Science+Business Media Dordrecht 1999 ASIC.SoC.Usability.V
描述.Reuse Techniques for VLSI Design. is a reflection on thecurrent state of the art in design reuse for microelectronic systems.To that end, it is the first book to garner the input of leadingexperts from both research and application areas. These expertsdocument herein not only their more mature approaches, but also theirlatest research results. .Firstly, it sets out the background and support from internationalorganisations that enforce System-on-a-Chip (SoC) design by reuse-oriented methodologies. This overview is followed by a number oftechnical presentations covering different requirements of the reusedomain. These are presented from different points of view, i.e., IPprovider, IP user, designer, isolated reuse, intra-company orinter-company reuse. More general systems or case studies, e.g.,metrics, are followed by comprehensive reuse systems, e.g., reusemanagement systems partly including business models. .Since design reuse must not be restricted to digital components,mixed- signal and analog reuse approaches are also presented. Inparallel to the digital domain, this area covers research in reusedatabase design. Design verification and legal aspects are twoimportant topics that
出版日期Book 1999
關(guān)鍵詞ASIC; SoC; Usability; VLSI; database; database design; integrated circuit; model; single-electron transistor
版次1
doihttps://doi.org/10.1007/978-1-4615-5159-1
isbn_softcover978-1-4613-7349-0
isbn_ebook978-1-4615-5159-1
copyrightSpringer Science+Business Media Dordrecht 1999
The information of publication is updating

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Hard IP Reuse Methodology for Embedded Cores, block. Improvements are desirable in the areas of synthesis constraints and ease of use, but the basic capabilities required to design a chip including soft IP do exist. This is almost true also for hard IP, if the block is treated like a big standard cell. Modifications to the design system are on
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Aspects of Reuse in the Design of Mixed-Signal Systems,ction. Therefore the design flow demands a well structured data organization. Not only the design flow but the design itself is improved by . of previously designed or verified data. Storage and organization has to be taken into consideration as well as the concrete interface between data and object
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Redesign of an MPEG-2-HDTV Video Decoder Considering Reuse Aspects, design methods and approaches. This leads to the increased application of block-oriented development techniques using proven designs, cores or components as basic building blocks which is referred to as design reuse. Of course, design reuse techniques such as providing cores or module generators ha
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