Titlebook: Reuse Methodology Manual for System-On-A-Chip Designs; Michael Keating,Pierre Bricaud Book 1998 Springer-Verlag US 1998 ASIC.RTL.Scratch.i

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System Integration with Reusable Macros,This chapter discusses the process of integrating completed macros into the whole chip environment. The topics are:

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System-Level Verification Issues,This chapter discusses system-level verification, focusing on the issues and opportunities that arise when macros are integrated into a complete system on a chip. The topics are:

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Data and Project Management,This chapter discusses tools and methodologies for managing the design database for macro design and for system design. The topics are:

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Implementing a Reuse Process,This chapter addresses requirements for establishing reuse processes within a company. These requirements include tools, process inventories, macro libraries, and pilot projects. Topics in this chapter include:

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Springer-Verlag US 1998

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Introduction,on onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available.

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Book 1998e gap between available gate-countand designer productivity. ..Reuse Methodology Manual for System-On-A-Chip Designs. outlinesan effective methodology for creating reusable designs for use in aSystem-on-a-Chip (SoC) design methodology. Silicon and tooltechnologies move so quickly that no single meth

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bridge the gap between available gate-countand designer productivity. ..Reuse Methodology Manual for System-On-A-Chip Designs. outlinesan effective methodology for creating reusable designs for use in aSystem-on-a-Chip (SoC) design methodology. Silicon and tooltechnologies move so quickly that no single meth978-1-4757-2887-3

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