| 書目名稱 | Reuse Methodology Manual |
| 副標題 | For System-on-a-Chip |
| 編輯 | Michael Keating,Pierre Bricaud |
| 視頻video | http://file.papertrans.cn/830/829341/829341.mp4 |
| 圖書封面 |  |
| 描述 | Silicon technology now allows us to build chips consisting oftens of millions of transistors. This technology not only promises newlevels of system integration onto a single chip, but also presentssignificant challenges to the chip designer. As a result, many ASICdevelopers and silicon vendors are re-examining their designmethodologies, searching for ways to make effective use of the hugenumbers of gates now available. .These designers see current design tools and methodologies asinadequate for developing million-gate ASICs from scratch. There isconsiderable pressure to keep design team size and design schedulesconstant even as design complexities grow. Tools are not providing theproductivity gains required to keep pace with the increasing gatecounts available from deep submicron technology. Design reuse -the use of pre-designed and pre-verified cores - is the mostpromising opportunity to bridge the gap between available gate-countand designer productivity. ..Reuse Methodology Manual for System-On-A-Chip Designs, SecondEdition. outlines an effective methodology for creating reusabledesigns for use in a System-on-a-Chip (SoC) design methodology.Silicon and tool technologies move so |
| 出版日期 | Book 1999Latest edition |
| 關(guān)鍵詞 | ASIC; RTL; Scratch; integrated circuit; system on chip (SoC); transistor |
| 版次 | 2 |
| doi | https://doi.org/10.1007/978-1-4615-5037-2 |
| isbn_softcover | 978-1-4613-7289-9 |
| isbn_ebook | 978-1-4615-5037-2 |
| copyright | Kluwer Academic Publishers 1999 |
|Archiver|手機版|小黑屋|
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