Titlebook: Reliable Software for Unreliable Hardware; A Cross Layer Perspe Semeen Rehman,Muhammad Shafique,J?rg Henkel Book 2016 Springer Internationa

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ovel optimization techniques for software cross-layer reliab.This book describes novel software concepts to increase reliability under user-defined constraints.? The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve in

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Introduction,on-critical, and airborne applications. The current and emerging generations of embedded computing systems pose stringent design constraints in terms of performance, area, power, and cost. Furthermore, there has been an increasing trend of applications’ functionality and even the number of applicati

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Background and Related Work,and aging-induced effects), the related work on soft error modeling, and their mitigation techniques. In particular, Sect. 2.1 provides the background regarding soft errors, starting with the basic transistor structure and its functionality, followed by various soft error sources and the soft error

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Software Program-Level Reliability Modeling and Estimation,er presents different reliability estimation models that are developed at different levels of granularity, i.e., instruction and function/task level. Since each system layer may employ distinct reliability optimization techniques that can operate at either the instruction or function/task level, it

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Software Program-Level Reliability Optimization for Dependable Code Generation,lity-driven compilation enabled by the instruction-level reliability models of Chap. . that quantify the reliability-wise importance of different instructions and the impact of their interdependencies on the vulnerability variations. This chapter presents several novel techniques for . in order to i

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Dependable Code Execution Using Reliability-Driven System Software,performance tradeoffs for optimization under constrained scenarios. This chapter presents several system software level reliability optimization techniques in order to enable dependable execution of applications on single core processors and multi-/manycore processors, while exploiting the concept o

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Results and Discussion,ns of this manuscript) compared to state-of-the-art single-layer reliability optimizing techniques. Evaluation of individual contributions compared to their relevant state-of-the-art techniques has already been presented in the respective chapters, i.e., Chaps. . and .. First the processor synthesis

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Summary and Conclusions, soft errors, design-time process variation, and run-time aging effects. In an on-chip manycore system, different cores may become subjected to diverse reliability threats, thereby ignoring one threat while mitigating the other threat might lead to designing a system with reliability inefficiencies.

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creased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers..978-3-319-79838-7978-3-319-25772-3