Titlebook: Reconfigurable Computing: Architectures and Applications; Second International Koen Bertels,Jo?o M. P. Cardoso,Stamatis Vassiliad Conferenc

洞穴

Efflorescent

Applications of Small-Scale Reconfigurability to Graphics Processorssed rather than replicated, yielding high-performance reconfigurable hardware with reduced area requirements. We show that SSR can be used effectively in programmable graphics architectures to allow double-precision computation without affecting the performance of single-precision calculations and t

pessimism

Pathogen

Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable P its hardware functionality within a clock cycle. While implementing an application on the DRP, designers face the task of selecting how to efficiently use resources in order to achieve particular goals such as to improve the performance, to reduce the power dissipation, or to minimize the resource

下級(jí)

Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chipgorithm and embedded in an AT94K40 system-on-chip device. This platform –composed of a 8-bit MCU that handles the program flow and a dynamically reconfigurable FPGA that synthesizes an evolvable slave coprocessor to speed up the calculus– provides a balanced control-computing architecture to efficie

bourgeois

Stricture

Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Casation-centric concept. Networks-on-chip (NoC) are good candidates providing both parallelism and flexibility. Nevertheless they imply to consider the notion of locality when distributing the computation among a set of cores. Defining an optimal placement at compile-time is difficult since other appl

受傷

impaction

Configurable Embedded Core for Controlling Electro-Mechanical Systemsl systems for typical light deflection purposes. An application is presented where the core is also applied for developing a complete image projection system. Experimental results show that an FPGA with modest resources, namely the ., is able to fulfill the basic requirements of these applications.

驕傲

Towards an Optimal Implementation of MLP in FPGA resources). This work addresses a complete study that compares the hardware implementation of MLP and a partially connected version (XMLP) in terms of computing speed, hardware resources and performance cost. Furthermore, we study also different memory management strategies for the connectivity patterns.