| 書目名稱 | Quick-Turnaround ASIC Design in VHDL | | 副標(biāo)題 | Core-Based Behaviora | | 編輯 | Mohamed S. Ben Romdhane,Vijay K. Madisetti,John W. | | 視頻video | http://file.papertrans.cn/782/781964/781964.mp4 | | 叢書名稱 | The Springer International Series in Engineering and Computer Science | | 圖書封面 |  | | 描述 | From the Foreword..... .Modern digital signal processing applications provide a largechallenge to the system designer. Algorithms are becoming increasinglycomplex, and yet they must be realized with tight performanceconstraints. Nevertheless, these DSP algorithms are often built frommany constituent canonical subtasks (e.g., IIR and FIR filters, FFTs)that can be reused in other subtasks. Design is then a problem ofcomposing these core entities into a cohesive whole to provide boththe intended functionality and the required performance. .In order to organize the design process, there have been two majorapproaches. The top-down approach starts with an abstract, concise,functional description which can be quickly generated. On the otherhand, the bottom-up approach starts from a detailed low-level designwhere performance can be directly assessed, but where the requisitedesign and interface detail take a long time to generate. In thisbook, the authors show a way to effectively resolve this tension byretaining the high-level conciseness of VHDL while parameterizing itto get good fit to specific applications through reuse of core librarycomponents. Since they build on a pre-designed set o | | 出版日期 | Book 1996 | | 關(guān)鍵詞 | ASIC; ASSP; Signal; VHDL; algorithm; algorithms; computer-aided design (CAD); design process; digital signal | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4613-1411-0 | | isbn_softcover | 978-1-4612-8612-7 | | isbn_ebook | 978-1-4613-1411-0Series ISSN 0893-3405 | | issn_series | 0893-3405 | | copyright | Kluwer Academic Publishers 1996 |
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