| 書目名稱 | Protecting Chips Against Hold Time Violations Due to Variability | | 編輯 | Gustavo Neuberger,Gilson Wirth,Ricardo Reis | | 視頻video | http://file.papertrans.cn/762/761568/761568.mp4 | | 概述 | Presents a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology.Studies the consequences of variability in several aspect | | 圖書封面 |  | | 描述 | .With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design..The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reason | | 出版日期 | Book 2014 | | 關(guān)鍵詞 | Digital Circuit Design; Efficiency; Testing; Variability | | 版次 | 1 | | doi | https://doi.org/10.1007/978-94-007-2427-3 | | isbn_softcover | 978-94-017-7794-0 | | isbn_ebook | 978-94-007-2427-3 | | copyright | Springer Science+Business Media Dordrecht 2014 |
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