| 書目名稱 | Principles of VLSI RTL Design |
| 副標題 | A Practical Guide |
| 編輯 | Sanjay Churiwala,Sapan Garg |
| 視頻video | http://file.papertrans.cn/756/755845/755845.mp4 |
| 概述 | Provides a highly accessible, single-source reference to all key topics essential to an RTL designer;.Describes in detail specific actions/cautions that designer needs to consider in design to avoid p |
| 圖書封面 |  |
| 描述 | Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written.? ?Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design. |
| 出版日期 | Book 2011 |
| 關(guān)鍵詞 | Clock Domain Crossing; RTL Design; Static Timing Analysis; VLSI Design |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4419-9296-3 |
| isbn_softcover | 978-1-4899-9545-2 |
| isbn_ebook | 978-1-4419-9296-3 |
| copyright | Springer Science+Business Media, LLC 2011 |
|Archiver|手機版|小黑屋|
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