| 書目名稱 | PLD Based Design with VHDL | | 副標(biāo)題 | RTL Design, Synthesi | | 編輯 | Vaibbhav Taraate | | 視頻video | http://file.papertrans.cn/741/740232/740232.mp4 | | 概述 | Presents a wealth of practical scenarios and case studies.Covers the synthesis and design implementation involved in using programmable ASICs.Includes the XILINX and ALTERA PLD architectures and appli | | 圖書封面 |  | | 描述 | This book covers basic fundamentals of logic design and advanced RTL design concepts using VHDL. The book is organized to describe both simple and complex RTL design scenarios using VHDL. It gives practical information on the issues in ASIC prototyping using FPGAs, design challenges and how to overcome practical issues and concerns. It describes how to write an efficient RTL code using VHDL and how to improve the design performance. The design guidelines by using VHDL are also explained with the practical examples in this book. The book also covers the ALTERA and XILINX FPGA architecture and the design flow for the PLDs. The contents of this book will be useful to students, researchers, and professionals working in hardware design and optimization. The book can also be used as a text for graduate and professional development courses.. | | 出版日期 | Book 2017 | | 關(guān)鍵詞 | ASIC prototyping; FPGA; SOC; STA; Synthesis | | 版次 | 1 | | doi | https://doi.org/10.1007/978-981-10-3296-7 | | isbn_softcover | 978-981-10-9836-9 | | isbn_ebook | 978-981-10-3296-7 | | copyright | Springer Nature Singapore Pte Ltd. 2017 |
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