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Titlebook: Offset Reduction Techniques in High-Speed Analog-to-Digital Converters; Analysis, Design and Pedro M. Figueiredo,Jo?o C. Vital Book 2009 Sp

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發(fā)表于 2025-3-21 19:43:21 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱Offset Reduction Techniques in High-Speed Analog-to-Digital Converters
副標(biāo)題Analysis, Design and
編輯Pedro M. Figueiredo,Jo?o C. Vital
視頻videohttp://file.papertrans.cn/701/700716/700716.mp4
概述All high-speed ADC architectures (flash, two-step, folding and interpolation) covered in detail.The performance parameters and trade-offs encountered in each of the ADC’s sub-blocks are analysed.Most
叢書名稱Analog Circuits and Signal Processing
圖書封面Titlebook: Offset Reduction Techniques in High-Speed Analog-to-Digital Converters; Analysis, Design and Pedro M. Figueiredo,Jo?o C. Vital Book 2009 Sp
描述.Offset Reduction Techniques in High-Speed Analog-to-Digital Converters?.analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. .
出版日期Book 2009
關(guān)鍵詞Analog-to-Digital Converter; Averaging; CMOS; Kickback noise; Offset Calibration; design automation
版次1
doihttps://doi.org/10.1007/978-1-4020-9716-4
isbn_softcover978-90-481-8192-6
isbn_ebook978-1-4020-9716-4Series ISSN 1872-082X Series E-ISSN 2197-1854
issn_series 1872-082X
copyrightSpringer Science+Business Media B.V. 2009
The information of publication is updating

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,Averaging Technique – DC Analysis and Termination,ng and interpolation ADCs there are analog preprocessing stages — folding circuits — whose differential pairs define the zero crossing locations. The mismatches in the elements of those circuits cause deviations on the location of the zero crossings, thus having a direct impact on the linearity of t
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Offset Cancellation Methods,g may accomplish a significant offset reduction, there are a number of tradeoffs (see sections 3.5.4 to 3.5.10) and practical limitations (for example signal headroom at low supply voltages) that restrict its effectiveness. Moreover, this technique is not applicable to latched comparators.. To ensur
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