Titlebook: Nanoscaled Semiconductor-on-Insulator Structures and Devices; Steve Hall,Alexei N. Nazarov,Vladimir S. Lysenko Conference proceedings 2007

Guffaw

書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices影響因子(影響力)




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices影響因子(影響力)學(xué)科排名




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices網(wǎng)絡(luò)公開度




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices網(wǎng)絡(luò)公開度學(xué)科排名




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices被引頻次




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices被引頻次學(xué)科排名




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices年度引用




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices年度引用學(xué)科排名




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices讀者反饋




書目名稱Nanoscaled Semiconductor-on-Insulator Structures and Devices讀者反饋學(xué)科排名

Ligneous

Status and trends in SOI nanodevicesulti-gate Si, SiGe, Ge and GaAs MOSFETs and Nanowires realized with various channel orientations are also addressed. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.

使迷醉

High-κ Dielectric Stacks for Nanoscaled SOI Devicess paper sets out the basic issues and physics associated with both hi- κ/metal gate and UTB from a device perspective, and establishes the advantages associated with merging the two approaches. A review of the state-of the art devices is undertaken also which serves to emphasize the great potential and progress of this technology.

ANTI

maintenance

SiGeC HBTs: impact of C on Device Performance?) on device performance. The devices with low C content (0.45?) exhibit excellent performance and gain up to 500. The results indicate that C content to be used in these devices should be less than 1?.

Retrieval

Popcorn

傾聽

Nanowire Quantum Effects in Trigate SOI MOSFETsnsconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section.

貪婪性

Substrate Effect on the Output Conductance Frequency Response of SOI MOSFETsrt the obtained results. It is demonstrated that the appearance of “substrate-related” transitions, their position and amplitude depend strongly on the substrate doping, space-charge conditions at substrate-BOX interface, temperature and moreover become more pronounced with device downscaling.

灰心喪氣