| 書目名稱 | Multi-GHz Frequency Synthesis & Division |
| 副標題 | Frequency Synthesize |
| 編輯 | Hamid R. Rategh,Thomas H. Lee |
| 視頻video | http://file.papertrans.cn/640/639950/639950.mp4 |
| 圖書封面 |  |
| 描述 | In the past 10 years extensive effort has been dedicated to commercial wireless local area network (WLAN) systems. Despite all these efforts, however, none of the existing systems has been successful, mainly due to their low data rates. The increasing demand for WLAN systems that can support data rates in excess of 20 Mb/s enticed the FCC to create an unlicensed national information infrastructure (U–NII) band at 5 GHz. This frequency band provides 300 MHz of spectrum in two segments: a 200 MHz(5.15–5.35 GHz) and a 100 MHz (5.725–5.825 GHz) frequency band. This newly released spectrum, and the fast trend of CMOS scaling, provide an opportunity to design WLAN systems with high data rate and low cost. One of the existing standards at 5 GHz is the European high performance radio LAN (HIPERLAN) standard that supports data rates as high as 20 Mb/s. One of the main building blocks of each wireless system is the f- quency synthesizer. Phase–locked loops (PLLs) are universally used to design radio frequency synthesizers. Reducing the power consumption of the frequency dividers of a PLL has always been a challenge. In this book, we introduce an alternative solution for conventional flipflop |
| 出版日期 | Book 2001 |
| 關鍵詞 | CMOS; Phase; Standard; analog; analog circuit design; circuit; development; network; tables |
| 版次 | 1 |
| doi | https://doi.org/10.1007/b100811 |
| isbn_softcover | 978-1-4757-7500-6 |
| isbn_ebook | 978-0-306-48106-2 |
| copyright | Springer Science+Business Media New York 2001 |
|Archiver|手機版|小黑屋|
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