| 書目名稱 | Modeling of Electrical Overstress in Integrated Circuits |
| 編輯 | Carlos H. Díaz,Sung-Mo Kang,Charvaka Duvvury |
| 視頻video | http://file.papertrans.cn/637/636238/636238.mp4 |
| 叢書名稱 | The Springer International Series in Engineering and Computer Science |
| 圖書封面 |  |
| 描述 | Electrical overstress (EOS) and Electrostatic discharge (ESD)pose one of the most dominant threats to integrated circuits (ICs).These reliability concerns are becoming more serious with the downwardscaling of device feature sizes..Modeling of Electrical Overstressin. .Integrated Circuits. presents a comprehensive analysis ofEOS/ESD-related failures in I/O protection devices in integratedcircuits. .The design of I/O protection circuits has been done in a hit-or-missway due to the lack of systematic analysis tools and concrete designguidelines. In general, the development of on-chip protectionstructures is a lengthy expensive iterative process that involvestester design, fabrication, testing and redesign. When the technologyis changed, the same process has to be repeated almost entirely. Thiscan be attributed to the lack of efficient CAD tools capable ofsimulating the device behavior up to the onset of failure which is a3-D electrothermal problem. For these reasons, it is important todevelop and use an adequate measure of the EOS robustness ofintegrated circuits in order to address the on-chip EOS protectionissue. Fundamental understanding of the physical phenomena leading todevice f |
| 出版日期 | Book 1995 |
| 關(guān)鍵詞 | VLSI; development; integrated circuit; material; modeling; semiconductor; semiconductor devices; simulation |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-2788-6 |
| isbn_softcover | 978-1-4613-6205-0 |
| isbn_ebook | 978-1-4615-2788-6Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Kluwer Academic Publishers 1995 |
|Archiver|手機版|小黑屋|
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